In multi-conductor bus systems, such as data and address buses on computer motherboards, cross talk between signals on the bus may cause modal velocity changes that depend on the transmitted data pattern. These modal velocity changes may significantly degrade the timing margins of digital systems and substantially decrease the maximum data rate that the bus can support. The effect may be especially significant for conventionally four-layer motherboards that may be utilized by manufacturers to conform to cost and volume structures in the industry. These modal velocity changes may provide an incentive for manufacturers to transition from four-layer motherboards to six or eight layer motherboards to address margin and other issues related to the modal velocity of the data on buses.
However, generally the more layers that are required to manufacture a motherboard the more costly the motherboard may become. Given the extreme cost sensitivity in a computer industry, increasing the cost of a component such as motherboard may not be desirable.
Therefore, there is a continuing need to address modal velocity changes and other issues in multi-conductor systems.
It should be understood that although the following detailed description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly and be defined only as set forth in the accompanied claims.